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HD49323AF-01 cds/agc & 10-bit a/d converter ade-207-262a (z) 2nd edition apr. 1999 description the HD49323AF-01 is a cmos ic that provides ccd-agc analog processing (cds/agc) suitable for ccd camera digital signal processing systems together with a 10-bit a/d converter in a single chip. functions correlated double sampling agc sample hold offset compensation serial interface control 10-bit adc 3 v single operation (2.7 v to 3.6 v) power dissipation: 198 mw (typ) maximum frequency: 20 mhz (min) features good suppression of ccd output low-frequency noise is achieved through the use of s/h type correlated double sampling. a high s/n ratio is achieved through the use of a agc type amplifier, and high sensitivity is provided by a wide cover range. an auto offset circuit provides compensation of output dc offset voltage fluctuations due to variations in agc amplifier gain. agc, standby mode, offset control, etc., is possible via a serial interface. high precision is provided by a 10-bit-resolution a/d converter. version of hitachi? previous-generation hd49322bf with improved functions and performance, including in particular an approximately 3.0 db improvement in s/n.
HD49323AF-01 2 pin arrangement nc bias vrt vrm vrb av dd av ss testc testy cdsin av dd av ss pblk d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 nc 36 35 27 34 33 32 31 30 29 28 26 25 12 10 3456789 1112 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 (top view) vrm2 clp nc av dd av ss spsig spblk obp adclk dv dd dv ss oe av ss av dd nc nc av dd av ss cs sck sdata dv dd dv ss dv ss
HD49323AF-01 3 pin description pin no. symbol description i/o analog(a) or digital(d) 1 pblk pre-blanking pin i d 2 d0 digital output (lsb) o d 3 to 10 d1 to d8 digital output o d 11 d9 digital output (msb) o d 12 nc no connection pin 13 oe digital output enable control pin i d 14 dv ss digital ground (0 v) d 15 dv dd digital power supply (3 v) connect off-chip in common with av dd . ? 16 adclk adc conversion clock input pin i d 17 obp optical black pulse input pin i d 18 spblk black level sampling clock input pin i d 19 spsig signal level sampling clock input pin i d 20 av ss analog ground (0 v) a 21 av dd analog power supply (3 v) connect off-chip in common with dv dd . ? 22 nc no connection pin 23 clp clamp voltage pin connect a 0.22 m f or more capacitor between clp and av ss . ? 24 vrm2 reference voltage pin (for ccd offset cancel) a 25 av ss analog ground (0 v) a 26 av dd analog power supply (3 v) connect off-chip in common with dv dd . ? 27 cdsin cds input pin i a 28 testy test input pin-y i a 29 testc test input pin-c i a 30 av ss analog ground (0 v) a 31 av dd analog power supply (3 v) connect off-chip in common with dv dd . ? 32 vrb reference voltage pin 3 connect a 0.1 m f ceramic capacitor between vrb and av ss . ? 33 vrm reference voltage pin 2 connect a 0.1 m f ceramic capacitor between vrm and av ss . ? 34 vrt reference voltage pin 1 connect a 0.1 m f ceramic capacitor between vrt and av ss . ?
HD49323AF-01 4 pin description (cont) pin no. symbol description i/o analog(a) or digital(d) 35 bias internal bias pin connect a 24 k w resistor between bias and av ss . ? 36 nc no connection pin 37 av ss analog ground (0 v) a 38 av dd analog power supply (3 v) connect off-chip in common with dv dd . ? 39, 40 nc no connection pin 41 av dd analog power supply (3 v) connect off-chip in common with dv dd . ? 42 av ss analog ground (0 v) a 43 cs serial interface control input pin i d 44 sck serial clock input pin i d 45 sdata serial data input pin i d 46 dv dd digital power supply (3 v) connect off-chip in common with av dd . ? 47, 48 dv ss digital ground (0 v) d
HD49323AF-01 5 input/output equivalent circuit pin name equivalent circuit digital output d0 to d9 din dv dd stby or oe digital output digital input adclk obp spblk spsig cs sck sdata pblk oe digital input 70k w (typ) *1 analog input cdsin cdsin connected to vrm internally reference voltage input vrt vrm vrb vrm2 vrt vrm vrm2 - + - + vrb clamp clp clp connected to vrm internally av dd internal bias bias bias av dd note: 1. applies to oe and pblk.
HD49323AF-01 6 block diagram gain select clamp circuit spsig bias ganerator 10bit adc cdsin cds agc clp serial interface spblk obp adclk output latch circuit vrt vrm vrb d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sck sdata cs bias av dd dv dd av ss dv ss 23 17 44 45 43 35 2 3 4 5 6 7 8 9 10 11 32 33 34 16 19 18 27 testy vrm2 27 27 27 testc oe 11 pblk 17
HD49323AF-01 7 internal functions functional description cds (correlated double sampling) circuit agc gain selection (11-bit digital control) * 1 ? agc gain can be set in the range 0 db to 34.7 db on the (+) side, and ?.3 db to 0 db on the (? side by means of 11-bit serial data. automatic offset adjustment is possible for the ic? offsets (cds, agc, adc) by means of serial data control at power-on.* 1 digital output enable function pre-blanking function ? digital output can be fixed at 32 lsb cds offset cancel function note: 1. serial data control operating description figure 1 shows cds/agc +adc function block. gain select offset cancel 10bit adc cdsin testy testc cds spblk adclk spsig sdata agc serial interface d0 to d9 cs sck figure 1 cds/agc +adc function block 1. cds (correlated double sampling) circuit the ccd imaging element alternately outputs a black level (a-period signal) and a signal including the black level (b-period signal). the cds circuit extracts the differential voltage between the black level and the signal including the black level (see figure 4). black level sampling is performed at the rising edge of the spblk pulse, and signal level sampling is performed at the rising edge of the spsig pulse. this sequence of operations extracts the differential voltage between the black level and the signal including the black level, and supplies this to the next- stage agc circuit. 2. feed back clamp function the clamp level is set by means of 5-bit serial data. the setting range is 32 lsb to 56 lsb, in 1 lsb steps. a serial data value of 0 gives a 32 lsb setting, and a value of 24 gives a 56 lsb setting.
HD49323AF-01 8 3. agc circuit the agc gain is set by means of 11-bit serial data. the setting range is ?.3 db to 34.7 db. details of the data are given in the following section. the (? side gain setting uses setting codes ?1 to 0 in 0.0039-multiple steps, and the (+) side gain setting uses setting codes 0 to 1023 in 0.034 db steps. detailed specifications of HD49323AF-01 agc gain setting codes (1) to improve s/n, the ad input dynamic range has been extended to 1.4 v from the 1.0 v of the hd49322bf. (2) there are two agc gain ranges: (+) side 0 to 34.7 db linear gain amp. (0.034 db/step), and (? side 0 to ?.3 db ?ultiple?linear gain amp. (0.0039 multiple/step). cds agc adc range typ 1.4v 0v = 0 code 0.7v = 511 code 1.4v = 1023 code output input considering the case where agc gain is set so that the adc output code is 511 when a 150 mv signal is input: ? the hd49322bf agc gain setting is (code 511)/150 mv multiple = 500 mv/150 mv multiple ? the HD49323AF-01 agc gain setting is (code 511)/150 mv multiple = 700 mv/150 mv multiple table 2 agc gain ( - ) setting code table table 1 agc gain (+) setting code table code bin (d10 to d0) db 0 000 0000 0000 0.000 3 000 0000 0011 0.102 2 000 0000 0010 0.068 1 000 0000 0001 0.034 510 001 1111 1110 17.34 513 010 0000 0001 17.44 512 010 0000 0000 17.41 511 001 1111 1111 17.37 1020 011 1111 1100 34.68 1023 011 1111 1111 34.78 1022 011 1111 1110 34.75 1021 011 1111 1101 34.71 code bin (d10 to d0) multiple 0 000 0000 0000 1.000 - 3 111 1111 1101 0.988 - 2 1111 1110 0.992 - 1 111 111 1111 1111 0.996 - 30 111 1110 0010 0.883 - 33 111 1101 1111 0.871 - 32 111 1110 0000 0.875 - 31 111 1110 0001 0.879 - 78 111 1011 0010 0.695 - 81 111 1010 1111 0.684 - 80 111 1011 0000 0.688 - 79 111 1011 0001 0.691 db 0.000 - 0.102 - 0.068 - 0.034 - 1.083 - 1.199 - 1.160 - 1.121 - 3.156 - 3.304 - 3.255 - 3.205 4. offset cancel circuit when power is turned on, offset voltages generated by cds, agc, adc, and other circuits by means of serial data control are canceled. (refer to page 24 (operating sequence at power-on).)
HD49323AF-01 9 5. digital output enable function when the oe pin is driven high, digital output goes to the high-z state. oe pin digital output high high-z state low (or open, gnd) output enable 6. pre-blanking function when the pblk pin is driven high, digital output is fixed at 32 lsb. however, this is valid only when the oe pin and serial data output mode settings (linv, minv, test, stby) are low. pblk pin digital output high fixed at 32 lsb low (or open, gnd) active 7. ccd offset cancel function this function cancels the offset voltage (v ofccd ) during the optical black period of the ccd imaging element. the definition of the ccd offset voltage (v ofccd ) is given below. the difference between the black level sampling voltage and signal level sampling voltage during the obp period is designated v ofccd . this value is positive when (signal level sampling voltage) > (black level sampling voltage). input signal for one pixel (during obp period) signal level sampling point black level sampling point cds input v ofccd (at +) v ofccd (at - ) figure 2 black level signal level difference during obp period table 3 serial data settings v ofccd cancel function when used when not used serial data settings vofcon bit set to 1 vofd0? (4 bits) set vofcon bit cleared to 0
HD49323AF-01 10 determining serial set data vofd0? (1) provisional setting serial data vofd0? settings are made according to the value of v ofccd as shown in table 4. (2) actual setting the set data is adjusted so that the clp pin (pin 23) voltage is closest to 1/2 av dd when agc gain is set to the maximum. the data obtained in (2) is used as the serial set data. table 4 v ofccd serial setting data correspondence table (for reference) v ofccd serial setting data (mv) vofd3 vofd2 vofd1 vofd0 ?10 0 0 1 0 9000 11 7001 00 5001 01 3001 10 1001 11 +1010 00 +3010 01 +5010 10 +7010 11 +9011 00 +110 1 1 0 1
HD49323AF-01 11 timing chart figure 3 shows the output timing. 0123456 n+1 n+2 n+3 n+4 n+5 n+6 n n - 4 n - 5n - 3n - 2n - 1n cdsin spblk spsig adclk d0 to d9 sampling timing chart figure 3 output timing the adc output signals (d0 to d9) are output at the rising edge of adclk. the pipeline delay is 5 clocks. h period obp > 12fs regarding obp note: the phase of obp is for a low setting of the serial data obp inv bit.
HD49323AF-01 12 details of timing specifications details of timing specifications details of the timing specifications are shown in figure 4, and the timing specifications are summarized in table 5. cds input spblk 1.4v (2) (3) serial data sp inv bit "lo" setting spsig adclk (7) 1.4v 1.4v (8) a period (4) (1) (5) (6)-2 (6)-1 (6)-1 (6)-2 b period cds input spblk 1.4v (2) (3) serial data sp inv bit "hi" setting spsig 1.4v adclk 1.4v (7) (8) a period (4) (1) (5) b period figure 4 details of timing specifications
HD49323AF-01 13 table 5 each timing specifications no. timing symbol min typ max unit note (1) black level signal read-in time t cds1 0510ns1 (2) spblk ?o?period t cds2 11 1/4f adclk typ 1.2 ns 2 (3) signal level read-in time t cds3 0510ns1 (4) spsig ?o?period t cds4 11 1/4f adclk typ 1.2 ns 2 (5) spblk rise to spsig rise t cds5 20 1/2f adclk typ 1.15 ns 2 (6)-1 adclk rise to spblk rise t cds6-1 25 ns 2 (6)-2 spsig rise to adclk rise t cds6-2 0ns2 (7), (8) adclk t wh min / t wl min t cds7, 8 22 ns note: 1. negative when data before the rising edge of spblk/spsig is sampled, and positive when data after the rising edge is sampled. 2. the polarity of spblk and spsig is for a low setting of the serial data sp inv bit. spblk spsig + - 1.4v detailed timing specifications for digital output enable control detailed timing specifications in the case of digital output enable control are shown in figure 5. when the oe pin is high, output disable mode is entered and output goes to the high-z state. digital output (d0 to d9) oe t lz t zl t hz t zh 1.4v dv dd 3.0v dv dd /2 dv dd /2 dv dd 2k w 10pf dv dd dv ss dv ss v ol t lz , t zl measurement load t hz , t zh measurement load v oh dv ss 10pf 2k w dv ss figure 5 detailed timing specifications for digital output enable control
HD49323AF-01 14 detailed timing specifications for pre-blanking detailed timing specifications for pre-blanking are shown in figure 6. when the pblk pin is high, digital output is fixed at 32 lsb. however, the oe pin and serial data output mode settings (linv, minv, test, stby) take precedence. digital output (d0 to d9) pblk t pblk t pblk 1.4v dv dd 3.0v v ol v oh figure 6 detailed timing specifications for pre-blanking
HD49323AF-01 15 output code table table 6 function table oe h stby x operation mode digital output output hi-z low power standby d0 d1 d2 d3 d4 d5 hi-z d6 d7 d8 d9 pblk x minv x linv x test x in the table 7 below, d9 to d0 are inverted l h h in the table 7 below, d8 to d0 are inverted l l h l in the table 7 below, d9 is inverted l h l normal operation table 7 as follows l l l l h l h l h l h l h x h h l h l h l h l h l l x l h h h l h l h l h l h h x h l test mode pre-blanking h l h l h l h l h l x l l l l l l l l l h l l l l h l l h hi-z x x x x note: 1. stby, test, linv, and minv mode setting is performed by means of serial data. 2. oe and pblk mode setting is performed by means of external input pins. 3. pre-blanking mode is enabled when the pblk pin is high and all other pins are low. table 7 output code table input level output pin l l l l l l l l l l d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 0 1 output code h ? 0v ? 0.7v ? 1.4v h h h h h h h h h l h h h h h h h h h h l h h h h h h h h l l h h h h h h h h step 512 511 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 1023 1022 1021 1020 2 h h h h h h h h h l h h l l l l l l l l l l l l l l l l l h h l l l l l l l l l l h l l l l l l l l
HD49323AF-01 16 absolute maximum ratings (ta = 25 c) item symbol ratings unit power supply voltage v dd(max) 6.0 v power dissipation p d(max) 400 mw analog input voltage v in(max) ?.3 to av dd +0.3 v digital input voltage v i(max) ?.3 to 6.0 v operating temperature topr ?0 to +85 c storage temperature tstg ?5 to +125 c note: 1. v dd indicates av dd and dv dd . 2. common connection of av dd and dv dd should be made off-chip. if av dd and dv dd are isolated by a noise filter, the phase difference should be 0.3 v or less at power-on and 0.1 v or less during operation.
HD49323AF-01 17 electrical characteristics (unless othewide specified, ta = 25 c, av dd = 3.0 v, dv dd = 3.0 v, r ext = 24 k w ) item symbol min typ max unit test conditions remarks power supply voltage range v dd 2.70 3.00 3.60 v f clk = 20 mhz conversion f clk max 20 mhz frequency f clk min 5.5 mhz digital input voltage v ih dv dd 3.0 2.0 5.0 v 5 v amplitude input possible v il 0 dv dd 3.0 0.8 v digital input pins except cs, sck, and sdata v ih2 dv dd 3.0 2.25 5.0 v 5 v amplitude input possible v il2 0 dv dd 3.0 0.6 v cs, sck, sdata digital output v oh dv dd ?.5 v i oh = ? ma voltage v ol 0.5 v i ol = +2 ma digital input current i ih 50 m av ih = 5.0 v digital input pins except pblk and oe i ih2 250 m av ih = 5.0 v pblk, oe i il ?0 m av il = 0 v digital output i ozh 50 m av oh = v dd current i ozl ?0 m av ol = 0 v adc resolution res 10 10 10 bit adc integration linearity error inl 4 10 lsbp-p f clk = 20 mhz adc differentiation dnl+ 0.3 0.8 lsb f clk = 20 mhz *1 linearity error dnl ?.8 ?.3 lsb digital output delay time t pd 35 ns c l = 10 pf digital output hold time t hold 10 ns note: 1. dnl calculate the difference of linearity error between next two codes.
HD49323AF-01 18 electrical characteristics (unless othewide specified, ta = 25 c, av dd = 3.0 v, dv dd = 3.0 v, r ext = 24 k w ) (cont) item symbol min typ max unit test conditions remarks sleep current i slp ?00 0 100 m a digital input pins fixed at 0 v, output pins open standby current i stby 8 12 ma digital input pins fixed at 0 v adc input range v inp-p (1.4) v *2 digital output hi-z t hz 100 ns r l = 2 k w *3 delay time t lz 100 ns c l = 10 pf t zh 100 ns t zl 100 ns digital output pblk delay time t pblk 100 ns c l = 10 pf *3 quiescent current i dd1 ?678 maf clk = 20 mhz cdsin use timing specification (1) t cds1 0 5 10 ns *3 timing specification (2) t cds2 11 1/4f adclk typ 1.2 ns timing specification (3) t cds3 0 5 10 ns timing specification (4) t cds4 11 1/4f adclk typ 1.2 ns timing specification (5) t cds5 20 1/2f adclk typ 1.15 ns timing specification (6-1) t cds6-1 25 ns timing specification (6-2) t cds6-2 0ns timing specification (7) t cds7 22 ns timing specification (8) t cds8 22 ns input current iin cds ?0 10 m af c lk = 20 mhz, black/signal level difference = 1 v, gain = 0 db *4 clamp level clp(00) (32) lsb *2 clp(16) (48) lsb clp(24) (56) lsb note: 2. items in parentheses are reference values. 3. refer to page 12 (details of timing specifications). 4. this is not transition current, but static current.
HD49323AF-01 19 electrical characteristics (unless othewide specified, ta = 25 c, av dd = 3.0 v, dv dd = 3.0 v, r ext = 24 k w ) (cont) item symbol min typ max unit test conditions remarks agc gain(? agc(?81) ?.3 ?.3 ?.3 db agc(0000) ?.0 0 2.0 db agc gain(+) agc(0000) ?.0 0 2.0 db agc(0128) 2.4 4.4 6.4 db agc(0256) 6.7 8.7 10.7 db agc(0384) 11.1 13.1 15.1 db agc(0512) 15.4 17.4 19.4 db agc(0640) 19.8 21.8 23.8 db agc(0768) 24.1 26.1 28.1 db agc(0896) 28.5 30.5 32.5 db agc(1023) 32.3 34.8 37.8 db
HD49323AF-01 20 serial interface specification sck cs sdata di 00 di 01 di 02 di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 sdata latched at rise of sck *1 *2, 3 data fixed at rise of cs t int 1 t ho t su t int 2 f sck note: 1. 2. 3. sdata is latched at the rise of sck. input 16 sck clocks while cs is low. if the number of clocks is more or less than 16, the data will be invalid. if data transmission is aborted, the data is invalid. figure 7 serial interface specification
HD49323AF-01 21 table 8 serial data functions table di 00 (lsb) lo lo di 01 hi hi hi lo hi resister 2 resister 0 resister 3 resister 1 lo di 02 di 03 di 04 di 05 di 06 di 07 di 08 di 09 di 10 di 11 di 12 di 13 di 14 di 15 (msb) low low low high low high high high agc gain setting (lsb) lo ? normal operation mode hi ? offset cancel mode ofrst lo ? reset mode hi ? normal operation mode reset lo ? off * 3 hi ? on vofcon lo ? f clk > 10mhz hi ? f clk < 10mhz cif lo ? negative input hi ? positive input obp inv sp inv spsig/spblk inversion vofd3 (msb) ccd offset voltage setting lo ? normal operation mode * 1 hi ? sleep mode slp clamp level adjustment (lsb) clamp level adjustment (msb) clamp level adjustment clamp level adjustment clamp level adjustment low test mode * 2 agc gain setting agc gain setting agc gain setting agc gain setting agc gain setting agc gain setting agc gain setting vofd2 ccd offset voltage setting vofd1 ccd offset voltage setting vofd0 (lsb) ccd offset voltage setting agc gain setting agc gain setting agc gain setting (msb) test mode low setting * 2 output mode setting (test) output mode setting (minv) output mode setting (linv) test mode low setting * 2 output mode setting (stby) * 1 test mode * 2 use prohibited all low stby: reference voltage generation circuit is in the operational state. slp: all circuits are in the sleep state. test mode is used for ic testing, and so cannot be used. register 2 test mode should be set in accordance with the specification at the right of the column. for other registers, the setting should only be made in the all-low state. setting of vofcon t su t ho t int 1, 2 f sck 50ns 50ns timing specifications 50ns ? min ? ? ? 3mhz max obp polarity h period obp > 12fs obp inv setting = lo negative h period obp > 12fs obp inv setting = hi positive notes: 1. 2. 3. : lo ? ccd offset cancel function off : hi ? ccd offset cancel function on
HD49323AF-01 22 notice for use 1. careful handling is necessary to prevent damage due to static electricity. 2. this product has been developed for consumer applications, and should not be used in non-consumer applications. 3. as this ic is sensitive to power line noise, the ground impedance should be kept as small as possible. also, to prevent latchup, a ceramic capacitor of 0.1 m f or more and an electrolytic capacitor of 10 m f or more should be inserted between the ground and power supply. 4. common connection of av dd and dv dd should be made off-chip. if av dd and dv dd are isolated by a noise filter, the phase difference should be 0.3 v or less at power-on and 0.1 v or less during operation. 5. if a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below. HD49323AF-01 av ss dv ss av dd dv dd noise filter analog +3.0v HD49323AF-01 dv ss av ss dv dd av dd 100 m h 0.01 m f noise filter example of noise filter digital +3.0v 0.01 m f 6. connect av ss and dv ss off-chip using a common ground. if there are separate analog system and digital system set grounds, connect to the analog system. 7. when v dd is specified in the delivery specification, this indicates av dd and dv dd . 8. no connection (nc) pins are not connected inside the ic, but it is recommended that they be used as power supply ground pins or left open to prevent crosstalk in adjacent analog pins. 9. to ensure low thermal resistance of the package, a cu-type lead material is used. as this material is less tolerant of bending than fe-type lead material, careful handling is necessary. 10. the infrared reflow soldering method should be used to mount the chip. note that general heating methods such as solder dipping cannot be used. 11. depending on the mounting state, picture quality (crosscut noise, wave pattern, etc.) will be dependent upon the timing of the spblk, spsig, and adclk signals. check the mounting state thoroughly before use. 12. serial communication should not be performed during the effective video period, since this will result in degraded picture quality. also, use of dedicated ports is recommended for the sck and sdata signals used in the HD49323AF-01. if ports are to be shared with another ic, picture quality should first be thoroughly checked. 13. at power-on, automatic adjustment of the offset voltage generated from cds, agc, adc, etc., must be implemented in accordance with the power-on operating sequence (see page 24).
HD49323AF-01 23 14. if the phase difference between the black level sampling voltage and the signal level sampling voltage during the ccd imaging element optical black period (the ccd offset voltage) is 30 mv or greater, the ccd offset cancel function (page 9, item 7, ccd offset cancel function) must be implemented. the ccd offset voltage variation after implementation of the ccd offset cancel function should be within 20 mv. 15. the cdsin pin is clamped at vrm ( @ av dd /2) during operation. the ic may suffer permanent damage if used with a pin voltage in the range ?.3 v to av dd + 0.3 v. careful attention must therefore be paid to the input signals.
HD49323AF-01 24 operating sequence at power-on reset v dd ofrst HD49323AF data transfer (2) reset = "hi" 1v(16ms) or more 4v(64ms) or more (4) ofrst = "hi" spblk spsig adclk obp etc. (1) reset = "lo" (5) ofrst = "lo" 0ms or more 0ms or more 0ms or more 0ms or more tg and camera dsp control start note: must be stabilized within operating power supply voltage range 0ms or more 1. 2. 3. reset and ofrst both use serial data transmission. stable input of spblk, spsig, adclk, and obp is assumed before reset is transmitted. numbers in parentheses in the figure show the order of transfer. (3) data transfer (6) data transfer figure 8 operating sequence at power-on serial data transmission contents are shown in table 9. ??indicates data for which the clock polarity, clamp level, etc., can be selected. see page 21 (table 8, serial data functions table) for the purpose of the data. table 9 serial data order of transfer (1) reset = "lo" remarks serial data (di) msb lsb 00 01 02 03 04 05 06 07 08 09 0 0 x x x x x x x x 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 x x x x x x x x 0 1 x x x x x 0 0 0 1 0 x x x x x x x x 4 v (64 ms) or more 1 v (16 ms) or more 1 0 x x x x x x x x (2) reset = "hi" (6) data transfer (5) ofrst = "lo" wait (4) ofrst = "hi" wait (3) data transfer 10 11 12 13 14 15 x x x x x 0 0 0 0 0 0 0 a) 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 b) c) d) 0 0 0 1 1 0 e) 0 0 0 1 0 0 g) f)
HD49323AF-01 25 example of recommended external circuit r2 220 r3 220 r4 220 r1 220 c19 0.1 c18 0.1 l1 47 m c6 0.1 cds/agc function is used (oe control and pre-blanking function are not used) av ss av dd nc nc av dd av ss cs sck sdata dv dd dv ss dv ss nc d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pblk vrm2 clp nc av dd av ss spsig spblk obp adclk dv dd dv ss oe av ss av dd cdsin testy testc av ss av dd vrb vrm vrt bias nc 23 26 27 28 29 30 31 32 33 34 c12 0.1 c13 0.1 c14 0.1 c15 0.1 35 36 25 11 10 9 8 7 6 5 4 3 2 1 12 16 15 14 13 17 18 19 20 c4 15p 21 22 24 38 45 46 47 48 44 43 42 41 40 39 37 serial data input gnd digital 3.0v from timing generator to camera signal processor from ccd out analog 3.0v c20 0.1 c7 1.0 c8 0.1 c9 1/16 r5 24k c5 15p c3 15p c2 15p c1 0.1 c17 47/6 c21 47/6 l2 47 m + - ha49323af-01 (cds/agc/adc)
HD49323AF-01 26 package dimensions preliminary hitachi code jedec eiaj weight (reference value) fp-48c ? conforms 0.2 g unit: mm *dimension including the plating thickness base material dimension 9.0 0.2 7.0 *0.21 0.05 0.08 36 25 112 37 48 24 13 0.5 9.0 0.2 0.10 1.00 0 - 8 0.50 0.10 *0.17 0.05 1.70 max m 0.75 0.75 0.19 0.04 1.40 0.15 0.04 0.13 +0.09 - 0.05
HD49323AF-01 27 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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